The present invention relates to improved methods and apparatus for chemical treatment of wafer, and particularly to improved methods and apparatus for precision bright etching of semiconductor wafers, i.e., acid etching of circular silicon wafers.
Sawed, lapped or ground silicon slices (wafers) are chemically etched primarily for the purpose of removing surface layers in which the crystals lattice structure has been disturbed by the preceeding rough mechanical shaping operation. Such damage, if not removed, can result in serious degradation of the bulk crystal structure in subsequent thermal treatment. In addition to removing damage, etching provides the additional benefits of:
1. A reduction in the mechanical distortion (bow) of the wafer caused by a difference in damage-induced stress on the two surfaces of the wafer;
2. Rounding of sharp wafer edges;
3. Improved cleanliness and ability to clean wafers; and
4. Improved wafer strength.
The latter two benefits are the result of elimination of surface cracks which are believed to harbor debris and serve as stress concentration points.
Mixtures of concentrated nitric acid, hydrofluoric acid and acetic acid are most often used in silicon etching. The nitric and hydrofluoric acids enter into the etching reaction directly as shown below in equation (1) while the acetic acid is added as a diluent which slows the reaction rate but improves the etched surface appearance (smoothness). EQU 3Si + 4HNO.sub.3 + 18HF .fwdarw. 3H.sub.2 SiF.sub.6 + 4NO + 8H.sub.2 O (1)
bright etching (or "etch polishing") occurs when relatively low concentrations of HF are employed so that the etching rate is limited by the rate of diffusion of HF to the silicon surface. This results in a selective attack on high points (probably because they extend into the diffusion gradient region) and produces a surface smoothing action. At higher HF concentrations, the attack is not selective and a dull or "flat" finish is produced.
Etching of slices by the prior art "bucket" or "tumble" etching method has always been characterized by a high degree of variability of stock removal both within batches (95% .+-. 0.3 mil) and between batches (95% .+-. 0.70 mils).
The within-batch variation is attributed largely to wafer-to-wafer differences in surface damage as well as failure to keep wafers completely separated by the manual agitation techniques typically employed.
The overriding factor in batch-to-batch variation appears to be the effect of temperature. The etching reaction is strongly exothermic, liberating 6150 calories per gram of silicon dissolved. Under the normal bucket etching conditions, this corresponds to an etchant temperature rise of about 64.degree.F for the nominal two-mil removal (or 128.degree.F rise for four-mil removal). As a result, the instantaneous etching rate is 3-4 times higher near the end of the run than at the beginning, making timing very critical. Also, for a fixed etching time, the total stock removal can vary considerably depending on the rate of temperature rise of the system. This, in turn, depends on the initial etch rate (which is affected by the starting temperature and degree of surface damage), the agitation, and the ratio of etchant volume to slice area. In the prior art, these factors have not been closely controlled.
Other problems with the prior art etching process include:
1. staining; PA1 2. high acid usage; PA1 3. poor within-wafer thickness uniformity; PA1 4. possibility of scratch damage through wafer contact during and after etching; PA1 5. high peak loads on fume scrubbing equipment; and PA1 6. excessive dilution of the spent etchant reduces efficiency of fluoride precipitation waste disposal system.
Heretofore, in the production processing of silicon wafers, the prior art "tumble etching" process has resulted in a broad thickness distribution of etched slices. This has required that a lapping of the etched wafers be carried out prior to finish polishing. Since there is a potential for significant yield and labor cost improvement in the polishing of wafers if the standard lapping step can be eliminated, it is desired that the etching technique provide improved thickness control in etching of the sliced silicon wafers.